A parallel analog-to-digital converter comprises a plurality of comparators for comparing an analog signal with an analog reference voltage, and an encoder for converting the signals output from the comparators to a digital signal.
The parallel analog-to-digital converter is superior to other types of analog-to-digital converters in terms of the analog-to-digital conversion speed. FIG. 1 shows a first conventional parallel analog-to-digital converter which produces two output bits. Four resistors R are connected in series between a high-potential reference voltage VRH and a low-potential reference voltage VRL. The resistance value of the resistor at each end is set to one-half that of the other resistor.
Each of the nodes among the resistors is connected to one of two input terminals of each of three comparators CM1 to CM3. Reference voltages VR1 to VR3 (which are obtained by division of the voltage difference between the reference voltages VRH and VRL by the resistances of the resistors R) are input, respectively, to the comparators CM1 to CM3. An analog input signal Vin is input to the other input terminal of each of the comparators CM1 to CM3. The comparators CM1 to CM3 compare, respectively, the reference voltages VR1 to VR3 with the analog input signal Vin. When the analog input signal Vin has a potential higher than the corresponding reference voltage VRl to VR3, the comparators CM1 to CM3 output, respectively, high-level output signals SG1 to SG3. In contrast, when the analog input signal Vin has a potential lower than the corresponding reference voltage VR1 to VR3, the comparators CM1 to CM3 output, respectively, low-level output signals SG1 to SG3.
If the analog input signal Vin has a potential higher than the reference voltage VR2 and a potential lower than the reference voltage VR3, the comparators CM1 and CM2 output the output signals SG1 and SG2 high, and the comparator CM3 outputs the output signal SG3 low. The output signals SG1 to SG3 form a thermometer code.
An encoder 3 receives the signals SG1 to SG3 and outputs two bits of digital output signals D0, D1. A control circuit 4 controls the timing of the comparators CM1 to CM3 and the encoder 3.
To ensure the accuracy of conversion regardless of a variation in the characteristics of the underlying transistors of the circuit, the comparators CM1 to CM3 preferably comprise, respectively, chopper type comparators. In the case of a CMOS comparator, an input offset voltage varies from comparator to comparator because of a variation in the characteristics of the MOS transistors. Such comparators produces an insufficiently accurate comparison result because of the variance in the input offset voltage.
FIG. 2 is a circuit diagram of the chopper type comparator. The input terminals, which receive the analog input signal Vin and the reference voltage VR, are connected to a node N1 (first terminal of a capacitor 1) via switching circuits SW1 and SW2. The switching circuits SW1 and SW2 are turned on in response to the control signals C1 and /CZ high. The second terminal of the capacitor 1 (a node N2) is connected to an input terminal of an inverter circuit 2a. Input and output terminals of the inverter circuit 2a are connected to each other via a switching circuit SW3. The switching circuit SW3 is turned on in response to the control signal CZ high.
In an auto-zero operation, the input and output terminals of the inverter circuit 2a are reset to a threshold value of the inverter circuit 2a. The output terminal of the inverter circuit 2a is connected to an input terminal of an inverter circuit 2c via an inverter circuit 2b and a switching circuit SW4. The switching circuit SW4 is turned on in response to the control signal /CF high. The signal output from the inverter circuit 2c is inverted by an inverter circuit 2e and output as a signal OUT. Further, the signal output from the inverter circuit 2c is fed back to the inverter circuit 2c via an inverter circuit 2d and a switching circuit SW5. The switching circuit SW5 is turned on in response to the control signal CF high.
The operation of the chopper type comparator will be described with reference to FIG. 3. First, when the control signal C1 goes high, and the control signal /CZ goes low, through the auto-zero operation, the node N2 is reset to the threshold value of the inverter circuit 2a, so that a charging current flows into the capacitor 1, thereby increasing the potential of the node N1 to the reference voltage VR. Subsequently, when the control signal C1 goes low, and the control signals /CZ and /CF go high, the analog input signal Vin is compared with the reference voltage VR. If the analog input signal Vin has a potential higher than the reference voltage VR, the potential of the node N2 becomes higher than the threshold value of the inverter circuit 2a as a result of capacitive coupling of the capacitor 1. In contrast, if the potential of the analog input signal Vin is lower than the reference voltage VR, the potential of the node N2 becomes lower than the threshold value of the inverter circuit 2a. Since the switching circuit SW4 is turned on at this time, the signal output from the inverter circuit 2a is provided to the inverter circuit 2c via the inverter circuit 2b and the switching circuit SW4. The signal output from the inverter circuit 2c is output as the signal OUT via the inverter circuit 2e.
Next, when the control signal C1 goes high again, and the control signals /CZ and /CF go low, the potential of the node N1 is reset to the reference voltage VR. Through the auto-zero operation performed by the inverter circuit 2a, the potential of the node N2 is reset to the threshold value of the inverter circuit 2a. At this time, the switching circuit SW5 is turned on, so that the inverter circuits 2c and 2d form a latch circuit which latches the signal OUT.
The chopper type comparator alternately performs the auto-zero operation and the comparing operation. Accordingly, one-half of the time required for the converting operation is spent on the auto-zero operation, thereby decreasing the conversion speed. Increasing the frequencies of the control signals C1, CZ, /CZ, CF, and /CF makes it difficult to perform the auto-zero operation and the comparing operation. Accordingly, it is not easy to increase the conversion speed of analog-to-digital conversion by increasing the frequencies of the control signals C1, CZ, /CZ, CF, and /CF.
If the number of comparators is increased in order to increase the number of bits of the digital output signal, noise is apt to arise in the reference voltage VR, the analog input signal Vin, and the power source which causes erroneous operation of the comparator. At the time of the auto-zero operation a charge/discharge current simultaneously flows between the reference voltage VR and the capacitor C1, and the input and output terminals of the inverter circuit 2a are concurrently reset to the threshold value. Consequently, a through current simultaneously flows through the inverter circuits 2a. Furthermore, at the time of the comparing operation, a charge/discharge current simultaneously flows between the analog input signal Vin and of each of the capacitors 1.
To increase the conversion speed of the chopper type comparator, a technique of controlling the control signals C1, CZ, /CZ, CF, and /CF at the timing shown in FIG. 4 has been proposed. More specifically, after the auto-zero operation, the control signals C1, CZ, and /CZ are maintained in the state of a comparing operation, and the control signals CF and /CF are inverted several times to thereby sample, e.g., analog input signals VA and VB. As a result, the comparing operation is performed several times on the basis of one auto-zero operation. This is because the comparing operation can be performed several times until the electric charge stored in the capacitor 1 during the auto-zero operation discharges completely. The ratio of the time required for the comparing operation to the time required for the auto-zero operation is increased, the conversion speed is increased.
However, there still remains the need for separate time required by all the comparators to simultaneously perform the auto-zero operation, and the noise caused at the time of the auto-zero operation is not prevented. Furthermore, the number of times of the comparing operation is limited.
Japanese Patent Application Laid-Open No. 8-293795 describes an IAZ (Interleaved Auto-Zero) analog-to-digital converter having four chopper type comparators which output e.g., digital output signals D1 and D0. The four comparators are selected in turn one at a time and caused to perform the auto-zero operation, while the comparison operation is performed by each of the other three comparators. Each comparator performs the comparing operation several times on the basis of one auto-zero operation. Since the analog-to-digital converter performs the auto-zero operation in parallel with the comparing operation, the operating speed is increased. Since the comparators do not all perform the auto-zero operations simultaneously, the noise resulting from the auto-zero operation is suppressed.
However, in the IAZ analog-to-digital converter, switching noise, which occurs when each of the comparators proceeds from the comparing operation to the auto-zero operation, causes an error in the comparing operation performed immediately before auto-zero operation. Furthermore, switching noise, which occurs when each of the comparators proceeds from the auto-zero operation to the comparing operation, causes an error in the comparing operation performed immediately after the auto-zero operation. Furthermore, when the comparators each proceed to the auto-zero operation from the comparing operation, the comparators may fail to latch and output the result of the comparison performed immediately before the auto-zero operation. Further, the limitation on the response speed of the comparator itself with respect to the switching from the reference voltage to the analog input signal does not provides an accurate comparison result obtained by the comparing operation immediately after the auto-zero operation. These problems degrade the error rate of the analog-to-digital converter when the respective comparator is operated at high speed.